Industry Voices: Implementing New Zonal Architecture in Advanced Automotive SOCs with IP

TU-Editor

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1st September 2021

Opinion piece by Ron DiGiuseppe, automotive IP segment manager with Synopsys.

The automotive industry is experiencing a shift in electrical/electronic (EE) system architecture which will impact automakers, Tier 1 and Tier 2 suppliers over the next 10 years.

The new EE system architecture, called “zonal architecture,” will alter both hardware (HW) systems and the associated software (SW) stacks, and is transitioning from legacy distributed ECU system to domain-based architecture and ultimately to zonal architecture, as shown in Figure 1.  Each EE system architecture implements the latest applications such as ADAS/highly automated driving (HAD), infotainment, chassis/body and powertrain. However, the combination of new applications and evolving system architecture is creating a new generation of sensors and System-on-Chips (SoCs) with very high performance, increased levels of integration, new hosted applications and increased amounts of AI.

The transition from distributed ECU system to current domain-based architecture and finally to zonal-based systems has had a significant impact in the automotive industry.  As early as 2019, Christian Senger, who oversaw Volkswagen’s digital activities stated VW’s goal is to reduce the electronic control modules (ECUs) from 70 to three ^1.  running SW to support the various applications on the centralized processing modules. More recently, Christophe Marnat, the executive vice-president of ZF’s electronics and ADAS products stated: “Trend toward centralization is there and we see all the OEMs working on this topic right now.”²

Figure 1 Evolution of electrical/electronic (EE) system architectures

Although, figure 1 shows the transition to centralized processing module as a straightforward event, the realization within the automotive industry will occur incrementally with certain OEMs investing more aggressively into the new platforms and applications.  It is estimated that multiple hybrid architectures will appear over time to achieve a centralized system.  Examples of hybrid architectures shown in Figure 2 illustrate hybrid architectures with centralized compute modules and additional domain modules which have not yet been integrated into the centralized module.  The hybrid implementations show how integration of all domain processing will occur in steps to allow a smooth transition to updated platforms and structured development for HW and SW suppliers.

Figure 2 Example Hybrid Architectures

The new zonal-based EE system architecture provides a number of benefits to OEMs compared to the existing domain-based architecture.  The current EE architecture with domain controllers and a central gateway have become very complex especially in terms of the wiring harness.  The wiring harness, connecting the domain-based system, is the 3^rd heaviest part of the car up to 80 kg with an absolute length up to 5km.  The installation of the wiring harness is also the 3^rd highest cost component owing to the amount of manual labor of up to 1,000+ production minutes.  New ADAS/HAD applications such as automatic emergency braking, lane keep aid and adaptive cruise control have increased the number of sensors and actuators with a dramatic increase in the data bandwidth required for the wiring harness, increasing the number of point-to-point connections.  The increased number of sensors significantly increases data and processing performance for the associated applications.  For example, each camera sensor may require between .5 – 3.5 Gbps data bandwidth to capture the image necessary to execute ADAS/HAD applications.  A 1080p image with a color depth of 24-bits at 30 frames per second (fps) will require 1.493 Gbps data bandwidth per camera sensor.  Considering Waymo’s HAD system can include up to 29 cameras³ the processing capabilities of the ADAS/HAD systems can quickly exceed the bandwidth capability of existing domain-based architectures without adding new channels in the wiring harness.  Adding the additional data from radar and lidar sensors significantly increases the sensor fusion processing and application processing performance.

The implementation of zonal architectures with a centralized compute module will impact the semiconductor SoCs which make up the vehicle EE systems.  A new generation of zonal gateway SoCs supporting multiple automotive channel protocols such as CAN, MIPI and automotive Ethernet ports running Ethernet Time Sensitive Networking (TSN) protocol will be required. The higher data rate of 10G-Base-T1 automotive Ethernet is planned to be used since the zonal gateways will aggregate data traffic for the automotive in-car Ethernet network.  By using the Ethernet TSN protocol, high priority safety-critical data packets can be transferred based on network policies to ensure lower priority data such as rear-seat entertainment does not interfere with safety-critical applications.

In addition to the zonal gateway SoCs, a new generation of centralized compute modules with multiple high-performance processors are required to execute the real-time, simultaneous applications. Since multiple real-time applications are running simultaneously, the processing SoCs used in the centralized compute modules must support virtualization similar to high performance smartphone processors or data center server processors.  Some industry observers consider the high-performance processing trends in automotive the “Smartphonezation” of the car. Since the SoCs must support multiple real-time applications, the SW stacks for the applications will need to be optimized for the new generation of high-performance automotive processors being developed. Forward planning and optimizing the HW to host the application SW will allow automakers to design the future SW Defined Vehicles and allow the introduction of new application-specific business models. However, for the high-performance SoCs targeting zonal central computing, the processors must include specialized functionality to meet the performance necessary to run the real-time applications.

One key design feature for a centralized compute zonal processing module is scalable heterogeneous multicore processors with up to 12 64-bit application processors integrated into the SoCs.  Even with x12 64-bit processors, the SoCs need additional accelerators to execute the applications due to the high degree of the required AI, which is a necessary function in multiple automotive applications.  OEMs are using AI for multiple applications in ADAS/HAD such as path planning, object/scene detection and recognition and AI-based decisions making. The ADAS/HAD applications previously mentioned such as automatic emergency braking, lane keep aid and adaptive cruise control are all AI based.  To meet application performance targets, industry analysts, Yole Development stated the performance required for HAD applications are in the range of a thousand Tera Operations per Second (TOPS) ⁴.  Current level 2/level 2+ ADAS systems are operating in the range of several hundred TOPS which highlights the improvement necessary to execute AI in a centralized compute module. In addition to AI-based ADAS/HAD, AI is appearing in domain applications such as infotainment driver monitoring systems (DMS) and heads-up display clusters.  AI is also in electric vehicle powertrain applications such as data analytics for virtual sensors plus in internal combustion engine management and E-mobility and chassis control to perform state prediction of lithium-ion batteries using AI/Deep Learning. With the increased adoption of AI, the SoC must integrate multiple AI accelerators in addition to the array of 64-bit application processors.

Considering the amount of virtualized applications processing, AI acceleration and DSP processing required to operate on multiple types of sensor data, the compute processor will require advance semiconductor manufacturing to implement the SoCs.  To meet the functional, integration and performance targets, advanced FinFET class semiconductor manufacturing processes such as automotive-grade 7nm or 5nm is required.  Figure 3 shows a general example for a central compute processor SoC with the typical functionality which can be implemented via IP.   The SoC contains up to 12 64-bit application processors and an AI-based vision subsystem for camera-based AI applications.  In addition to the required processing performance, the SoC contains a separate ISO 26262 functional safety manager and an independent security subsystem to minimize security vulnerabilities.  A complete suite of connectivity interfaces provides multiple channels to connect to the SoC, to the in-car zonal network as well as to the additional point-to-point protocols such as MIPI and CAN. Finally, we see two High-Performance Computing (HPC) interfaces, PCI Express (PCIe) and Compute Express Link (CXL), that are used to expand the processing performance of the SoC by adding separate SoC accelerators to achieve multi-SoC performance.   PCI Express is the dominant peripheral protocol to connect multiple SoCs to add algorithm accelerators to increase SoC performance.

Figure 3 Central Compute Processor SoC

Designers are leveraging automotive-grade IP during the zonal architecture evolution to ensure SoC-level capability, bandwidth and power requirements.  64-bit processors and interface IP such as PCI Express, CXL, LPDDR, MIPI and Ethernet with TSN features that are compliant with the ISO 26262 functional safety standard provide the compute requirements which SoCs must implement for the next stage of automotive platform architecture.

References

1 Christian Senger, Volkswagen Group board of management member, September 2019

2 Christophe Marnat, EVP ZF Electronics/ADAS, May 2021

3 YooJung Ahn, Head of Design at Waymo, March 2020

4 Yole Development, March 2020